By Rakesh Chadha
This e-book presents a useful primer at the strategies used in the layout of low strength electronic semiconductor units. Readers will enjoy the hands-on strategy which begins shape the ground-up, explaining with uncomplicated examples what energy is, the way it is measured and the way it affects at the layout technique of application-specific built-in circuits (ASICs). The authors use either the Unified energy structure (UPF) and customary strength structure (CPF) to explain intimately the ability reason for an ASIC after which advisor readers via quite a few architectural and implementation thoughts that may aid meet the ability rationale. From studying procedure strength intake, to recommendations that may be hired in a low energy layout, to an in depth description of 2 trade criteria for shooting the ability directives at quite a few levels of the layout, this e-book is full of info that may provide ASIC designers a aggressive aspect in low-power design.
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Extra resources for An ASIC Low Power Primer: Analysis, Techniques and Specification
This chapter describes each of these contributions in detail—specifically the factors affecting the power calculation from various contributions in the design. Switching activity formats are also described in this chapter. 1 What Is Switching Activity? As described in Chaps. 2 and 3, the power computation is generally obtained from the power models included in the library descriptions of the standard cells, memory macros and the IO libraries. This computation of power using library power models relies upon the transition activity and state of each pin of standard cells, memory macros and the IOs.
The transition rate is also referred to as toggle rate. For periodic signals such as clocks where the frequency of the signal is specified, the transition rate is twice the frequency of the signal (since there are two transitions—rising and falling—within each cycle). The power analysis utilizes the switching activity (static probability and transition rate) for each signal in the design. 3 Examples In Fig. 1, the probability that pins CK and Q are at 1 is 50%. However, the toggle rate for pin CK is 8 toggles in 40 ns, or 200 million transitions per second.
4 43 Summary Fig. 5 0 Note that the above computation holds for DC power dissipated within the IO and it applies when the source is high or when the source is low. Similar to the case described in previous subsection, the power sourced by the VDDQ supply of the IO buffer is an entirely different computation from the above. 4. Similar to the case described in previous subsection, the power dissipated in the IO is different from the power sourced by the VDDQ supply of the IO buffer. Similar to the output mode, the power description in the Liberty models is normally not adequate for accurate power analysis in input mode also.