By Ricardo Martins, Nuno Lourenço, Nuno Horta
This publication introduces readers to various instruments for analog structure layout automation. After discussing the situation and routing challenge in digital layout automation (EDA), the authors review quite a few automated format new release instruments, in addition to the newest advances in analog layout-aware circuit sizing. The dialogue comprises diversified tools for computerized placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The thoughts and algorithms of all of the modules are completely defined, permitting readers to breed the methodologies, enhance the standard in their designs, or use them as place to begin for a brand new device. the entire tools defined are utilized to sensible examples for a 130nm layout strategy, in addition to placement and routing benchmark sets.
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Extra resources for Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques
The approach automatically analyzes legacy design data including circuits, layouts, and constraints, and generates multiple layouts for the new design by reutilizing the legacy information as much as possible. In , Po-Cheng Pan proposes a mechanism to extract the relationship among wires and design blocks, and that information can then be used for complete layout migration. Not only the behavior of the old designs is preserved, but several metrics for multiple placement generation and wire refinement are included within this process to improve the quality of the resultant layout prototyping.
In  both current-flow and current-density constraints are addressed at the placement stage by modeling cell’s devices and interconnects in an enhanced HB*-tree representation. A constructive dynamic programming-based global router simultaneously place and route the modules, and, reserves routing space between cells. 4 Optimization Algorithm of Choice: Simulated Annealing SA  is one of the most popular stochastic techniques, and is used in most of the optimization-based floorplan approaches for analog design automation proposed in the last decades.
Many of the circuits manufactured today are the ones developed and implemented years ago, so it is extremely important to take advantage of the knowledge embedded in their layouts and follow the advances in the integration technologies, instead of going through all the design process again. For this, the idea of parameterized model/template is present in the most recent successful approaches in the past few years. Increasing the designer’s active part in the generation of the floorplan is not necessarily a drawback, since the inclusion of his knowledge increases the floorplan quality and allows the tool to easily generate a solution that fully meets analog designers’ expectations/needs.