By Mehdi Dehbashi, Görschwin Fey
This ebook describes automatic debugging methods for the insects and the faults which seem in numerous abstraction degrees of a process. The authors hire a transaction-based debug method of platforms on the transaction-level, announcing the proper relation of transactions. the automatic debug technique for layout insects reveals the capability fault applicants at RTL and gate-level of a circuit. Debug recommendations for good judgment insects and synchronization insects are tested, allowing readers to localize the main tough insects. Debug automation for electric faults (delay faults)finds the doubtless failing speedpaths in a circuit at gate-level. many of the debug methods defined in achieving excessive analysis accuracy and decrease the debugging time, shortening the IC improvement cycle and extending the productiveness of designers.
- Describes a unified framework for debug automation used at either pre-silicon and post-silicon stages;
- Provides ways for debug automation of a procedure at various degrees of abstraction, i.e., chip, gate-level, RTL and transaction level;
- Includes strategies for debug automation of layout insects and electric faults, in addition to an infrastructure to debug NoC-based multiprocessor SoCs.
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Extra info for Debug Automation from Pre-Silicon to Post-Silicon
The X value of F C can be propagated through jBGj jF Gj different paths. The method activates individual paths to more likely reduce the intersection with paths related to other fault candidates. As shown in Fig. b2 ; mb2 ; mb1 ; F C ; mf1 ; mf2 ; f1 / indicated by bold arrows. For propagating the X value of F C through the path P , the following constraints are required (Fig. 3) using controlling and non-controlling values as explained in Sect. 1 on Page 10: – The off-path inputs of each gate mfi 2 M G, i D 1; 2; : : : ; jM Gj, have to have a ncv.
Before reaching the forward nodes for F C , there are some middle nodes which are collected in the set M G, and the forward nodes are collected in the set F G. 3 shows an example of a circuit graph. Considering F C , the sets M G D fmf1 ; mf2 g and F G D ff1 ; f2 g result. Thus the number of forward nodes (forward branches) is jF Gj D 2. The backward nodes are collected in the set BG. The set BG for F C in Fig. 3 is BG D fb1 ; b2 g and thus the number of backward nodes (backward branches) is jBGj D 2.
One correction block is inserted at the output of each gate. The select lines of the correction blocks are controlled by the fault cardinality constraint. The debug instance is translated into CNF. A SAT solver is utilized to find and to enumerate all possible solutions (fault candidates). sel3 D 1; r3 D 0/. In this case, the NAND and OR gates are considered as fault candidates, as their corresponding multiplexers are the solutions found by the SAT solver. sel1 D 1; r1 D 0/ means if the select line sel1 is activated and the correction value r1 D 0 is inserted in the circuit, the correct output value is created.